XC3S200-4C

Product Summary

The XC3S200-4C is a Spartan-3 Field-Programmable Gate Array specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to five million system gates. The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from state-of-the-art Virtex-II technology. The XC3S200-4C combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Parametrics

XC3S200-4C absolute maximum ratings: (1)VCCINT, Internal supply voltage: -0.5 to 1.32 V; (2)VCCAUX, Auxiliary supply voltage: -0.5 to 3.00 V; (3)VCCO, Output driver supply voltage: -0.5 to 3.75 V; (4)VREF, Input reference voltage: -0.5 to VCCO+0.5 V; (5)VIN, Voltage applied to all User I/O pins and Dual-Purpose pins: -0.5 VCCO +0.5 V; Voltage applied to all Dedicated pins: -0.5 VCCAUX +0.5 V.

Features

XC3S200-4C features: (1)Very low cost, high-performance logic solution for high-volume, consumer-oriented applications, Densities as high as 74,880 logic cells; Three power rails: for core (1.2V), I/Os (1.2V to; (2)3.3V), and auxiliary purposes (2.5V); (3)SelectIO signaling, Up to 784 I/O pins; 622 Mb/s data transfer rate per I/O; 18 single-ended signal standards; 6 differential I/O standards including LVDS, RSDS; Termination by Digitally Controlled Impedance; Signal swing ranging from 1.14V to 3.45V; Double Data Rate (DDR) support; (4)Logic resources, Abundant logic cells with shift register capability; Wide multiplexers; Fast look-ahead carry logic; Dedicated 18 x 18 multipliers; JTAG logic compatible with IEEE 1149.1/1532; (5)SelectRAM hierarchical memory, Up to 1,872 Kbits of total block RAM; Up to 520 Kbits of total distributed RAM; (6)Digital Clock Manager (up to four DCMs), Clock skew elimination; Frequency synthesis; High resolution phase shifting; (7)Eight global clock lines and abundant routing; (8)Fully supported by Xilinx ISE development system, Synthesis, mapping, placement and routing; (9)MicroBlaze processor, PCI, and other cores; (10)Pb-free packaging options; (11)Low-power Spartan-3L Family and Automotive Spartan-3 XA Family options.

Diagrams